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Features
General
* High-performance, Low-power secureAVRTM RISC Architecture * * * * * *
- 135 Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to 6000V Operating Ranges: 2.7 to 5.5V Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible Available in Wafers, Modules, and Industry-standard Packages
Memory
* 128K Bytes of ROM Program Memory * 36K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Area
- 1 to 128-byte Program / Erase - 1.25 ms Program / 1.25 ms Erase - Typically More than 500,000 Write/Erase Cycles at a Temperature of 25oC - 10 Years Data Retention - EEPROM Erase Only Mode - Write EEPROM With or Without Autoerase * 5K Bytes of RAM * 32K Bytes of ROM Dedicated to Atmel's Crypto-library
Secure Microcontroller for Smart Cards AT90SC 12836RCT Summary
Peripherals
* One I/O Port * ISO7816 Controller * * * * * * * *
- Up to 625 kbps at 5 MHz - Compliant with T= 0 and T= 1 Protocols Programmable Internal Oscillator - Up to 20 MHz on ROM - Up to 40 MHz for Cryptographic Accelerator Two 16-bit Timers Random Number Generator (RNG) 2-level, 7-vector Interrupt Controller 32-bit Cryptographic Accelerator for Public Key Operations Including - RSA, DSA, ECC, Diffie-Hellman Hardware DES and Triple DES DPA Resistant Checksum Accelerator CRC 16 & 32 Engine (Compliant with ISO/IEC 3309)
Security
* * * * * * * *
Dedicated Hardware for Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack, Including Active Shield Environmental Protection Systems Voltage Monitor Frequency Monitor Light Protection Temperature Monitor Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
* Voyager Emulation Platform (ATV4) to Support Software Development * IAR Systems EWAVR(R) V3.10 Debugger or Atmel's AVR Studio(R) Version 4.07 or Above * Software Libraries and Application Notes
6508CS-SPD-15May07
Note: This is a summary document. A complete document will be available under NDA. For more information, please contact your local Atmel sales office.
Certification
* * * *
EAL4+ VISA CAST ZKA
Description
AT90SC12836RCT is a low power, high performance, 8/16-bit microcontroller based on the secureAVRTM enhanced RISC architecture, with ROM program memory and EEPROM data memory. By executing powerful instructions in a single clock cycle, the AT90SC12836RCT achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 generalpurpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The AT90SC12836RCT uses the secureAVRTM this allows the linear addressing of up to 8M bytes of code and up to 16M bytes of data as well as a number of new functional and security features. The AT90SC12836RCT includes 36K bytes of Atmel's high density, non volatile memory. The crypto engine featured in the AT90SC series is the AdvXTM, a 32-bit accelerator dedicated to perform fast encryption or authentication functions. Additional security features include power and frequency protection logic, logical scrambling on all data and addresses, Power Analysis countermeasures and memory accesses controlled by a supervisor mode. Figure 1 shows the AT90SC12836RCT block diagram. Figure 1. AT90SC12836RCT secureAVR RISC Architecture
Data Bus 8-bit OTP EEPROM User Memory ROM ATMEL Program Memory 16 Instruction Register 16 8 Instruction Decoder 16 Control Lines Status Register 8 General Purpose Registers X
Y Z CLK
Access Control
RNG
Secure Control
GND
VCC
AdvX CryptoCoprocessor Access Control
PC
RAM Data Memory Interrupt Unit
8
ALU
ISO 7816 Controller ISO 7816 I/O Port 0 Timer Reset Circuit DES DPA Counter measures CRC and Checksum Accelerator RST
IN/OUT0
2
AT90SC12836RCT
6508CS-SPD-15May07
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6508CS-SCIC-15May07

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